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nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 1 sp6339, sp6341 triple power supervisory circuit with manual reset and watchdog sp6339-sp6341 triple power supervisory c ircuit family is a family of microprocessor reset supervisory circuits with multiple reset voltages. the fam ily provides low voltage monitoring ability for up to three supplies with two precision factory-set thresholds and one user defined custom threshold. these circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. products in the family offer manual reset and watchdog functionalities. sp6339 and sp6341 are packaged in an 8-pin tsot package. all devices are fully specified over -40 o c to +85 o c temperature range. features low opera ting voltage of 1.6v low operating current of 20 a typical monitors up to 3 supplies simultaneously adjustable input monitors down to 0.5v reset asserted down to 0.9v 2% accuracy over temperature range open drain (od) or cmos rstb output 4 reset timeout periods: 50ms, 100ms, 200ms, and 400ms watch dog timer function -- wdi independent od or cmos watchdog output (active low) -- wdob manual reset input (active low) -- mrib 8 pin tsot package description now available in lead free packaging see page 2 for other available pinouts 1 2 3 4 5 6 7 8 8 pin tsot v2 sp6339 v1 wdi v3 mrib gnd wdob rstb open drain reset typical application circuit
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica - tions below is not implied. exposure to absolute maxi - mum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. terminal voltage (with respect to gnd) v1, v2.................................................... -0.3 to +6v open-drain rstb, wdob ..................................................... -0.3 to +6v cmos rst, rstb, wdob.... ...................................... . -0.3 to (v1+0.3v) feature and pinout diagram input current/output current...... ...........................,,.............. ..........20ma v3, mrib, wdi ........................ -0.3 to (v1+0.3v) operating temperature range ............................................... -4 0 c to +85 c storage temperature range...............................................-65 c to 150 c thermal resistance ja . .............................134 c/w part number v1 v2 v3 reset mrib wdi wdob sp6339 od active low od active low sp6341 cmos active low cmos active low 1 2 3 4 5 6 7 8 8 pin tsot v2 sp6339 v1 wdi v3 mrib gnd wdob rstb open drain reset 1 2 3 4 5 6 7 8 8 pin tsot v2 sp6341 v1 wdi v3 mrib gnd wdob rstb cmos reset representative samples available sipex product product description package v1 (volts) v2 (volts) v3 (volts) v4 (volts) reset (ms) ordering # sp6339 triple supervisor open drain low 8 pin tsot 4.625 2.313 0.5 n/a 200 sp6339ek1-l-z-j-c
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 3 electrical characteristics parameter min typ max units conditions operating voltage ran g e 0.9 5.5 v t a = -40oc to +85oc 20 30 ua v1 < 5.5v, v2 < 3.60v, all i/o pins open 15 25 v1 < 3.6v, v2 < 2.75v, all i/o pins open 4.532 4.625 4.718 z ( valid for v1 fallin g) 4.287 4.375 4.463 y ( valid for v1 fallin g) 3.013 3.075 3.137 x ( valid for v1 fallin g) 2.866 2.925 2.984 w ( valid for v1 fallin g) v1 reset 2.572 2.625 2.678 v ( valid for v1 fallin g) threshold 2.273 2.320 2.367 u ( valid for v1 fallin g) 2.146 2.190 2.234 t ( valid for v1 fallin g) 1.636 1.670 1.704 s ( valid for v1 fallin g) 1.548 1.580 1.612 r ( valid for v1 fallin g) 2.266 2.313 2.360 j ( valid for v2 fallin g) 2.144 2.188 2.232 i ( valid for v2 fallin g) 1.631 1.665 1.698 h ( valid for v2 fallin g) 1.543 1.575 1.607 g ( valid for v2 fallin g) v2 reset 1.360 1.388 1.416 f ( valid for v2 fallin g) threshold 1.286 1.313 1.340 e ( valid for v2 fallin g) 1.087 1.110 1.133 d ( valid for v2 fallin g) 1.029 1.050 1.071 c ( valid for v2 fallin g) 0.816 0.833 0.850 b ( valid for v2 fallin g) 0.772 0.788 0.804 a ( valid for v2 fallin g) threshold 1 tempco 0.06 mv/oc threshold 2 tempco 0.04 mv/oc threshold 1 h y steresis 0.65 % reference to vth1 typical threshold 2 h y steresis 0.5 % reference to vth2 typical v1 to rst/rstb dela y 50 us v1 = vth1 to (vth1-0.1v), vth1 = 3.075 v2 to rst/rstb dela y 50 us v2 = vth2 to (vth2-0.1v), vth2 = 1.575 reset timeout period ( t1 ) 37 50 63 ms topt-1 reset timeout period ( t2 ) 74 100 126 ms topt-2 reset timeout period ( t3 ) 148 200 252 ms topt-3 reset timeout period (t4) 296 400 504 ms topt-4 v v v1 = 1.6v to 5.5v; ta = -40oc to +85oc; unless otherwise noted. typical values are at ta =+25oc supply current
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 4 electrical characteristics parameter min typ max units conditions v3 in p ut threshold 490 500 510 mv v3 input current -50 50 na t a = +25oc v3 threshold h y steresis 1.5 mv mrib input threshold 0.4 v vil mrib input threshold 0.8*v1 v vih mrib minimum in p ut pulse width 1 us mrib glitch re j ection 150 ns mrib to rst/rstb dela y 100 ns mrib pull-up resistance 30 55 85 k? watchdog timeout period 1.2 1.6 2 sec wdi pulse width 0.1 us wdi input threshold 0.4 v vil wdi input threshold 0.8*v1 v vih wdi in p ut current -500 500 na wdi = 0.0v or v1 rstb (cmos or od) 0.4 v v1 = vth1 - 0.1v, isink = 1ma, out p ut asserted rstb (cmos) 0.8*v1 v v1 = vth1 + 0.1v, isource = 1ma, out p ut not asserted wdob (cmos or od) 0.4 v wdi = 0.0v or v1, v1 > vth1, v2 > vth2, v3 > 0.5, mrib float, isink = 1ma, wdob output asserted wdob (cmos) 0.8*v1 v v1 > vth1, v2 > vth2, v3 > 0.5, mrib float, wdob not asserted, isource = 1ma rstb / wdob output od leakage current 2 na t a = +25oc reset / watchdog outputs rstb / wdob wdi - watchdog input v1 = 1.6v to 5.5v; t a = -40oc to +85oc; unless otherwise noted. typical values are at t a =+25oc v3 reset comparator input mrib - manual reset input
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 5 pin description pin # name description 1 v1 first supply voltage input. also powers internal circuitry. trip threshold voltage internally set. 2 v2 second supply voltage input. trip threshold voltage internally set. 3 wdi watch-dog input pin. when no transition is detected at the wdi pin for the duration of wdi timeout period, reset is asserted. rstb output is used to signal watchdog timeout overflow -- rstb output pulses high/low (depending on the active reset polarity) for the reset timeout period after each watchdog timeout overflow. wdob remains at low logic level after watchdog timeout period is expired and it remains low until wdi makes a transition. rstb output is not affected by the watchdog functionality. the watchdog timer clears whenever the reset is asserted or manual reset is asserted or a transition is observed at wdi pin. 4 v3 input for the third supply voltage. trip threshold is 0.5v. 5 wdob watch dog output. open-drain or cmos, active low. if wdi remains at high or low logic level for longer than the watchdog timeout period, the internal watchdog timer overflows and wdob is asserted. wdob does not de-assert until the watchdog is cleared via transition at the wdi pin. another scenario for wdob to assert is when the reset output is asserted due to an under-voltage v1, v2, v3 condition. wdo de-asserts without a reset timeout period. floating wdi will not disable watchdog timer in devices with dedicated wdob output. open-drain wdob outputs require an external pull-up resistor. cmos outputs are referenced to v1. 6 gnd common ground reference pin. 7 mrib manual reset input pin. active low. it has an internal pull-up resistor. reset asserted when mrib is pulled low and is kept asserted for 200ms after mrib is released or pulled high. leave open if not used. 8 rstb reset output. open-drain or cmos, active low. reset is asserted when any of the three supply inputs is below its trip threshold. it stays asserted for 200 ms (typical / default) after the last supply input traverses its trip threshold. reset is guaranteed to be in the correct state for v1>0.9v. rstb asserts when v1 or v2 or v3 drop below their corresponding reset thresholds, or mrib is pulled low. rstb remains asserted for the reset timeout period after v1 and v2 and v3 exceed their corresponding reset thresholds or mrib goes low to high. open-drain outputs require an external pull-up resistor. cmos outputs are referenced to v1.
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 6 the sp6339 and sp6341 include a low- voltage precision bandgap reference, three precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. the family is designed to supervise up to 3 independent supply voltages. v1 and v2 supply inputs have their resistor dividers on the chip. their trip thresholds are factory trimmed. the v3 input allows users to customize an additional supply threshold to be monitored by means of an external resistor divider. the parts are furnished with manual reset and watchdog output functionalities. the watchdog functionality cannot be disabled. block diagram theory of operation osc wdi logic control logic v1 v2 v3 wdi rstb gnd 1.25v 0.5v mrib wdob band gap ref
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 7 figure 1: functionality of the sp6339 and sp6341. ? v1 > vth1, v2 > vth2 , and v3 > vth3 (all supplies over their corresponding thresh - olds)----> rstb is de-asserted after reset timeout period (trp) & wdob de-asserts immediately without waiting for reset timeout period. ? mrib goes to low to force reset ----> rstb is asserted immediately & wdob is not affected by mrib and is not asserted. ? wdi keeps making transitions within watchdog timeout period (t neither rstb nor wdob changes state. ? one of the supplies drops below its corresponding threshold (in this case v3) ----> rstb is asserted immediately & wdob is asserted immediately too. whenever v1, v2, v3 are below their specified thresholds wdob is asserted. theory of operation v1 v2 v3 vth1 vth2 vth3=0.5v mrib wdi rstb trp trp ttwd t nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corpora tion 8 v1 rstb resetb timeout period (400ms) application information sp6339watchdog timeout period v1 rstb wdi = gnd, v1=v2=v3=5v, mrib = open. watchdog timeout period = 1.52s
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 9 application information v1 and v2 glitch rejection v3glitch rejection v1 and v2 glitch rejection 0 50 100 150 200 250 0 20 40 60 80 100 120 overdrive (mv) d u r a t i o n ( u s ) rstb asserted above line v3 glitch rejection 0 20 40 60 80 100 120 0 20 40 60 80 100 120 overdrive (mv) d u r a t i o n ( u s ) rstb asserted above line
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 10 application information rstb vs. v1 (v2 = gnd) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v1 (vdc) r s t b ( v d c ) reset good reset timeout vs. temperature reset to (400ms) vs temperature 0 100 200 300 400 500 85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 deg c t i m e o u t ( m s )
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 11 package: 8 pin tsot front view l ? gauge plane l2 c r r1 ? ? seating plane side view a a1 a2 seating plane d e e/2 e1 3 2 1 b e e1 e1/2 5 4 pin1 designator to be within this index area (d/2 x e1/2) top view (l1) d/2 8 7 6 min nom max min nom max a - - 1.10 - - 0.043 a1 0.00 - 0.10 0.000 - 0.004 a2 0.70 0.90 1.00 0.028 0.036 0.039 c 0.08 - 0.20 0.003 - 0.008 d e e1 l 0.30 0.45 0.60 0.012 0.018 0.024 l1 l2 0? 4 8? 0? 4? 8 1 4? 10? 12? 4? 10? 12 r 0.10 - - 0.004 - - r1 0.10 - 0.25 0.004 - 0.010 b 0.22 - 0.38 0.009 - 0.015 e e1 1.95 bsc 0.60 ref 0.024 ref 1.60 bsc 0.063 bsc 0.077 bsc 0.65 bsc 0.026 bsc 0.25 bsc 0.010 bsc sipex pkg signoff date/rev: jl oct3-05 / rev a symbol 8 pin tsot jedec mo-193 variation ba 2.90 bsc 0.114 bsc 2.80 bsc 0.110 bsc dimensions in millimeters: controlling dimension dimensions in inches conversion factor: 1 inch = 25.40 mm
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 12 part naming nomenclature sp63nn - th1 - th2 - topt t1 -- 50 ms t2 -- 100 ms t3 -- 200 ms t4 -- 400 ms a -- 0.788 v b -- 0.833 v c -- 1.050 v d -- 1.110 v e -- 1.313 v f -- 1.388 v g -- 1.575 v h -- 1.665 v i -- 2.188 v j -- 2.313 v z -- 4.625 v y -- 4.375 v x -- 3.075 v w -- 2.925 v v -- 2.625 v u -- 2.320 v t -- 2.190 v s -- 1.670 v r -- 1.580 v 30 -- quad sp, mr, wdi, od rstb 31 -- quad sp, od rstb 32 -- quad sp, mr, wdi, cmos rstb 33 -- quad sp, cmos rstb 34 -- quad sp, mr, wdi, cmos rst 35 -- quad sp, cmos rst 36 -- triple sp, wdi, pf, od rstb 37 -- triple sp, wdi, pf, cmos rstb 38 -- triple sp, wdi, pf, cmos rst 39 -- triple sp, mr, wdi, od rstb - wdob 40 -- dual sp, wdi, od rstb - wdob 41 -- triple sp, wdi, pf, cmos rstb - wdob 42 -- dual sp, wdi, cmos rstb - wdob { { { a b c d e f g h i j k l m a b c d example: jzjd means: sp6339 in tsot-8 lead package v1 threshold is 4.625v v2 threshold is 2.313v reset timeout is 400ms jzjd pin 1
nov 20-06 rev j sp6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 13 ordering information model temperature range package type sp6339ek1-l-x-x-x.......................................-40 c to +85 c................................lead free 8-pin tsot sp6339ek1-l-x-x-x/tr.................................-40 c to +85 c................................lead free 8-pin tsot sp6341ek1-l-x-x-x........................................-40 c to +85 c................................lead free 8-pin tsot sp6341ek1-l-x-x-x/tr..................................-40 c to +85 c................................lead free 8-pin tsot available in lead free packaging only. /tr = tape and reel pack quantity 2,500 for tsot. contact factory for availability of particular voltage threshold and reset timeout options. note that the ordering information denoting those options corresponds to the part naming nomenclature shown on the previous page. ordering example: sp6339ek1-l-w-g-c/tr == w -- 2.925v for voltage threshold 1; g -- 1.575v for voltage threshold 2; and c -- 200ms reset timeout. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
datasheet appendix & web link information ? 2007 sipex corporation for further assistance: email: sipexsupport@sipex.com www support page: http://www.sipex.com/content.aspx?p=support sipex application notes: http://www.sipex.com/applicationnotes.aspx product change notices: http://www.sipex.com/content.aspx?p=pcn sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make change s to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither do es it convey any license under its patent rights no r the rights of others. the following sections contain information which is more changeable in nature and is therefore generated as appendices. 1) package outline drawings 2) ordering information if available: 3) frequently asked questions 4) evaluation board manuals 5) reliability reports 6) product characterization reports 7) application notes for this product 8) design solutions for this product solved by tm solved by tm appendix and web link information
partnernet advancedsearch part number search keyword search home products support contact us about us news investors careers product lines power management boostregulators buckregulators chargepumps leddrivers linearregulators powerblox? pwmcontrollers references supervisors usbvbusswitches interface multiprotocol rs232 rs422 rs485 usb optical storage advancedpower control photodetectoric sp6341 product details youarehere: home : products : supervisors :sp6341 features lowoperatingvoltageof1.6v lowoperatingcurrentof20uatypical monitorsupto3suppliessimultaneously adjustableinputsmonitordownto0.5v resetasserteddownto0.9v 2%accuracyovertemperaturerange cmosrstboutput 4resettimeoutperiods:50ms,100ms,200msand 400ms watchdogtimerfunctionalitywdi independentodwatchdogoutput(activelow) wdob 8pintsotpackage representativesamplesareavailableusingthesp6339 for v1=4.625v,v2=2.313v,v3=v4(factoryset)=0.5v and 200msresettimeout.****contactfactoryforavailab ility ofparticularthresholdandresettimeoutoptions.**** triple micropower supervisory circuit with manual reset and watchdog quick links download datasheet checkpriceand availability design- in support email:techsupport supervisorsproduct selector applicationsnotes evaluationboards qualityinformation partnomenclature sp6341faq ordering part number part number package code rohs min. temp. ( c) max. temp.( c) status buy sp6341 ek1l supervisorstriple sp6341 :contact factoryforvoltage options new! tsot8 ? 40 85 cf_ part status legend active thepartisreleasedforsale,standardproduct. eol (end of life) thepartisnolongerbeingmanufactured,there mayormaynotbeinventorystillinstock. cf (contact factory) thepartisstillactivebutcustomersshouldch eckwiththefactoryforavailability.longerlead timesmayapply. pre (pre-introduction) theparthasnotbeenintroducedorthepartnum berisanearlyversionavailableforsampleonly. obs (obsolete) thepartisnolongerbeingmanufacturedandmay notbeordered. nrnd (not recommended for new designs) thepartisnotrecommendedfornewdesigns. home | sitemap | termofuse | privacypolicy | contactus allrightsreserved,sipex2007 page 1 of 1 sipex corporation - sipex product details 8/15/2007 http://www.sipex.com/productdetails.aspx?part=sp634 1&keyword=sp6341

jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 1 of 6 introduction the primary function of a microprocessor ( p) supervisor circuit is to ensure that the input supply voltage of a microprocessor is at proper levels during power up, power down and brownout conditions. if the input su pply voltage to a microprocessor is below its required operating rang e, it could cause code- execution errors, memory corruption and latch up. t he supervisor will constantly monitor the input supply to the microprocessor, and in the event this supply voltage falls below a certain threshold, the reset output will be asserted. many of today?s power products require several different voltage rails for powering various components. the microprocessor itself can h ave a separate core voltage and logic voltage. other components such as dsps, a sics and microcontrollers can have their own unique voltage requirements. to service this demand of monitoring multi-voltage systems, sipex has develop ed the sp6330 family. the sp6330 family is a series of multi-voltage supervis ors that offer monitoring of up to 4 separate supplies and are equipped with specia lized features. a complete listing of products and features are listed in figu re 4 at the end of this note. sp6332 typical applications circuit for monitoring 4 supplies with master reset, watchdog input and cmos reset output rstb v1 v2 v3 v4 i/o r2 r3 r4 r5 0.1uf 0.1uf 0.1uf 0.1uf mr sp6332 v1 1 v2 2 mrib 3 v3 4 gnd 6 wdi 7 rstb 8 v4 5 supplies up c4 c3 c2 c1 monitored to be solved by tm application note anp14 understanding and selecting a multi-voltage supervisor f eaturing the sp6330 f amily
jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 2 of 6 inputs to the sp6330 family the sp6330 family has the ability to monitor up to 4 different voltages. two of these inputs (v1 and v2) have precision factory-set thresholds while the remaining two inputs (v3 and v4) are adjustable. v3 and v4 inputs allow the user to customize two additional supply thresholds by me ans of an external divider. the threshold for v3 and v4 inputs is 0.5volts. th e v1 input supplies power to the device and will have the highest threshold for a given application; its minimum operating voltage for is 1.8v. the factory set threshold range for v1 and v2 inputs are shown in figure 1. v1 typical threshold v2 typical threshold 4.625 2.313 4.375 2.188 3.075 1.665 2.925 1.575 2.625 1.388 2.320 1.313 2.190 1.110 1.670 1.050 1.580 0.833 0.788 figure 1 reset output ? rst or rstb the reset output can be either active low or active high depending on each device. the reset output can also be either open-dr ain or push-pull outputs. the open drain output requires an external pull-up resi stor to v1 for normal operation. the output high voltage (v oh ) of the reset output will be approximately equal t o the v1 input voltage. reset timeout period the reset timeout period is a built-in time delay f or the reset output. this timeout period is activated at power up or when all monitor ed voltages have risen above their respective thresholds. reset timeout period f or the sp6330 family is offered in four different time intervals: 50ms, 100ms, 200 ms and 400ms. the actual selection of timeout period depends on the applicat ions requirements of the system voltage settle time. the reset timeout perio d is used to ensure that all voltage rails and system clocks have stabilized pri or to executing code to prevent errors or data corruption.
jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 3 of 6 manual reset input (active low) ? mrib the manual reset input allows the user to manually trigger a reset when monitored voltages are within tolerance. this is us eful for resetting the microprocessor when it locks up due to software iss ues. a push-button type switch can be used to allow the user to trigger a r eset externally. however, since a push button switch will bounce several times, a d ebounce element is needed. the manual reset input signal may also be a logic s ignal from an i/o line, watchdog timer or a power fail output. watchdog input ? wdi the watchdog checks for proper software execution. if the software locks up or enters into an unwanted, loop the watchdog timer ca n either assert a reset output or a watchdog output. some members of the sp6330 fa mily offer a watchdog output while others do not. the watchdog has an int ernal timer that has a typical watchdog timeout period of 1.6 seconds. if the watc hdog input (wdi) does not detect a transition within 1.6 seconds, a reset or watchdog output (wdo) will be generated. the watchdog input is usually connected to an i/o line for monitoring software activity. the watchdog circuit is useful f or generating a reset or non- maskable interrupt (nmi) signal during software loc k up conditions without human intervention. floating the wdi will disable t he watchdog feature. watchdog output (active low) ? wdob the watchdog output is active low and can be either an open drain or push-pull output. if wdi remains at ?high? or ?low? logic lev el for longer than the watchdog timeout period, the internal watchdog time r overflows and the wdob will be asserted. additionally, if the reset output is asserted due to an under- voltage condition, at any voltage input the wdob wo uld also be asserted. floating wdi will not disable the watchdog timer in devices with dedicated wdob output. power fail input (pfi) the power fail input is used to monitor the unregul ated dc voltage or other upstream voltage and to alert the system that a bro wnout or power failure is imminent. when the pfi input is tripped, it can inf orm the system to start a power-down routine in order to save important data before a reset output is asserted. the power fail input has a threshold of 0 .5v. by using a voltage divider the user can monitor any upstream voltage. connect pfi to v1 or gnd if not used.
jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 4 of 6 power fail output (active low) - pfob the pfob pin is an open drain, active low output. w hen the input voltage at pfi is <0.5v, pfob will be asserted. r4 r5 r6 ri rstb v1 v3 v2 up i/o r2 r3 0.1uf 0.1uf 0.1uf unregulated dc monitored to be supplies c1 c3 c2 sp6336 v1 1 v2 2 pfi 3 v3 4 pfob 5 gnd 6 wdi 7 rstb 8 nmi sp6336 typical applications circuit for monitoring 3 supplies with power fail input / output function and open drain reset o utput glitch immunity at voltage inputs the v1, v2, v3 and v4 inputs have a built-in glitch immunity feature that prevents nuisance resets during normal operation. n oise and normal voltage transients can cause these unwanted resets without some type of glitch immunity. figure 2 shows the combination of voltage overdrive and duration that will not cause a reset for v1 and v2 inputs. figure 3 shows the same data as applied to the v3 and v4 inputs. adding a small byp ass capacitor to voltage inputs can improve glitch rejection for very harsh environments.
jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 5 of 6 figure 2 figure 3 v3 and v4 glitch rejection 0 20 40 60 80 100 120 0 20 40 60 80 100 120 overdrive (mv) duration (us) rstb asserted above line v1 and v2 glitch rejection 0 50 100 150 200 250 0 20 40 60 80 100 120 overdrive (mv) duration (us) rstb asserted above line
jun 27-06 sp6330 family: select ing a multi-voltage supervisor ? 2006 sipex corporation page 6 of 6 sp633x features ? quad, triple or dual supply monitoring ? very low operating voltage down to 1.6v ? low 20 a typical operating current ? adjustable inputs monitor down to 0.5v ? open drain or cmos reset outputs ? 4 reset timeout periods: 50ms, 100ms, 200ms and 40 0ms ? glitch immunity inputs ? tiny 6 pin or 8 pin tsot package p/n v1 v2 v3 v4 reset reset mrib wdi wdob wdob pfi pfob package output active od cmos sp6330 x x x x od low x x 8-tsot sp6332 x x x x cmos low x x 8-tsot sp6334 x x x x cmos high x x 8-tsot sp6331 x x x x od low 6-tsot sp6333 x x x x cmos low 6-tsot sp6335 x x x x cmos high 6-tsot sp6336 x x x od low x x x 8-tsot sp6337 x x x cmos low x x x 8-tsot sp6338 x x x cmos high x x x 8-tsot sp6339 x x x od low x x x 8-tsot sp6341 x x x cmos low x x x 8-tsot sp6340 x x od low x x 6-tsot sp6342 x x cmos low x x 6-tsot figure 4: product selection guide
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 1 fa q sp6330 - sp6342 dual/triple/quad po wer supervisory circuit f amily sp6330-sp6342 dual/triple/quad power supervisory circuit family is a family of microprocessor reset supervisory circuits with multiple reset voltages. the sp6330 family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. these circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. some of the products in the family offer manual reset,power fail and watchdog functionalities. the sp63xx family includes a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. v1 and v2 supply inputs have their resistor dividers on the chip. their trip thresholds are factory trimmed. v3 and v4 inputs allow user to customize two additional supply thresholds to be monitored by means of external resistor dividers. some members of the family are furnished with manual reset, power fail indication, watchdog functionalities.sp6330 thru sp6342 are housed in a 6-pin or 8-pin sot23 package. all devices are fully specified over -40 o c to +85 o c temperature range. features low operating voltage of 1.8v low operating current of 20 a typical monitors up to four supplies simultaneously adjustable inputs monitor down to 0.5v reset asserted down to 0.9v 2% accuracy over temperature range power fail function open drain (od) or cmos rstb output or cmos rst output 200ms reset timeout period watch dog timer function independent open drain watchdog output manual reset input sot23-6/8 packages description available in lead free packaging 1 2 3 4 5 6 7 8 8 pin sot-23 v2 sp6330 v1 mrib v3 wdi gnd v4 rstb open drain reset see page 3 for other available pinouts
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 2 part number v1 v2 v3 v4 reset manual reset input bar watchdog input watchdog output bar power fail input power fail output bar # of pins data- sheet group sp6330 - od active low - - - 8 1 sp6331 ??? od active low - - - - - 6 5 sp6332 - cmos active low - - - 8 1 sp6333 ??? cmos active low - - - - - 6 5 sp6334 - cmos active high - - - 8 1 sp6335 ??? cmos active high - - - - - 6 5 sp6336 - od active low - - 8 2 sp6337 - cmos active low - - 8 2 sp6338 - cmos active high - - 8 2 sp6339 - od active low od active low - - 8 3 sp6340 - - od active low - od active low - - 6 4 sp6341 - cmos active low cmos active low - - 8 3 sp6342 - - cmos active low - cmos active low - - 6 4 feature mapping diagram
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 3 pinout master diagram v1 v2 v1 v2 rstb wdi gnd v4 v1 v2 mrib v4 wdi rst gnd open drain rstb cmos rstb cmos rst v1 v2 v3 v4 rstb gnd open drain rstb v1 v2 v3 v4 rstb gnd cmos rstb v1 v2 v3 v4 rst gnd cmos rst v1 v2 v3 pfi wdi rstb gnd v1 v2 v3 pfi wdi rstb gnd v1 v2 v3 pfi wdi rst gnd open drain rstb cmos rstb cmos rst pfob pfob pfob v3 v1 v2 v3 wdi gnd rstb mrib wdob 1 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 8 1 2 3 45 6 7 81 2 34 5 61 2 34 5 61 2 34 5 6 1 2 3 45 6 7 8 sv02-sip1 mopt-b (sot23-6) 1 2 34 5 6 v1 v2 v3 wdi gnd rstb mrib wdob 1 2 3 45 6 7 8 v1 v2 wdi wdob rstb gnd 1 2 34 5 6 open drain rstb open drain rstb cmos rstb v1 v2 wdi wdob rstb gnd 1 2 34 5 6 cmos rstb v3 mrib v4 gnd wdi rstb v3 mrib sp6342 (sot23-6) sp6341 (sot23-8) sp6339 (sot23-8) sp6338 (sot23-8) sp6337 (sot23-8) sp6336 (sot23-8) sp6335 (sot23-6) sp6334 (sot23-8) sp6333 (sot23-6) sp6332 (sot23-8) sp6331 (sot23-6) sp6330 (sot23-8) sp6340 (sot23-6)
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 1 fa q sp6330 - sp6342 dual/triple/quad po wer supervisory circuit f amily sp6330-sp6342 dual/triple/quad power supervisory circuit family is a family of microprocessor reset supervisory circuits with multiple reset voltages. the sp6330 family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. these circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. some of the products in the family offer manual reset,power fail and watchdog functionalities. the sp63xx family includes a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. v1 and v2 supply inputs have their resistor dividers on the chip. their trip thresholds are factory trimmed. v3 and v4 inputs allow user to customize two additional supply thresholds to be monitored by means of external resistor dividers. some members of the family are furnished with manual reset, power fail indication, watchdog functionalities.sp6330 thru sp6342 are housed in a 6-pin or 8-pin sot23 package. all devices are fully specified over -40 o c to +85 o c temperature range. features low operating voltage of 1.8v low operating current of 20 a typical monitors up to four supplies simultaneously adjustable inputs monitor down to 0.5v reset asserted down to 0.9v 2% accuracy over temperature range power fail function open drain (od) or cmos rstb output or cmos rst output 200ms reset timeout period watch dog timer function independent open drain watchdog output manual reset input sot23-6/8 packages description available in lead free packaging 1 2 3 4 5 6 7 8 8 pin sot-23 v2 sp6330 v1 mrib v3 wdi gnd v4 rstb open drain reset see page 3 for other available pinouts
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 2 part number v1 v2 v3 v4 reset manual reset input bar watchdog input watchdog output bar power fail input power fail output bar # of pins data- sheet group sp6330 - od active low - - - 8 1 sp6331 ??? od active low - - - - - 6 5 sp6332 - cmos active low - - - 8 1 sp6333 ??? cmos active low - - - - - 6 5 sp6334 - cmos active high - - - 8 1 sp6335 ??? cmos active high - - - - - 6 5 sp6336 - od active low - - 8 2 sp6337 - cmos active low - - 8 2 sp6338 - cmos active high - - 8 2 sp6339 - od active low od active low - - 8 3 sp6340 - - od active low - od active low - - 6 4 sp6341 - cmos active low cmos active low - - 8 3 sp6342 - - cmos active low - cmos active low - - 6 4 feature mapping diagram
date: 5/3/06 sp6330-sp6342 dual/triple/quad power supervisory circuit family ? copyright 2006 sipex corpora tion 3 pinout master diagram v1 v2 v1 v2 rstb wdi gnd v4 v1 v2 mrib v4 wdi rst gnd open drain rstb cmos rstb cmos rst v1 v2 v3 v4 rstb gnd open drain rstb v1 v2 v3 v4 rstb gnd cmos rstb v1 v2 v3 v4 rst gnd cmos rst v1 v2 v3 pfi wdi rstb gnd v1 v2 v3 pfi wdi rstb gnd v1 v2 v3 pfi wdi rst gnd open drain rstb cmos rstb cmos rst pfob pfob pfob v3 v1 v2 v3 wdi gnd rstb mrib wdob 1 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 81 2 3 45 6 7 8 1 2 3 45 6 7 81 2 34 5 61 2 34 5 61 2 34 5 6 1 2 3 45 6 7 8 sv02-sip1 mopt-b (sot23-6) 1 2 34 5 6 v1 v2 v3 wdi gnd rstb mrib wdob 1 2 3 45 6 7 8 v1 v2 wdi wdob rstb gnd 1 2 34 5 6 open drain rstb open drain rstb cmos rstb v1 v2 wdi wdob rstb gnd 1 2 34 5 6 cmos rstb v3 mrib v4 gnd wdi rstb v3 mrib sp6342 (sot23-6) sp6341 (sot23-8) sp6339 (sot23-8) sp6338 (sot23-8) sp6337 (sot23-8) sp6336 (sot23-8) sp6335 (sot23-6) sp6334 (sot23-8) sp6333 (sot23-6) sp6332 (sot23-8) sp6331 (sot23-6) sp6330 (sot23-8) sp6340 (sot23-6)
reliability report: sp6330 april 7 , 2006 page 1 of 5 reliability and qualification report sp 6330 prepared by: g. west reviewed by: fred claussen manager, quality assurance vp quality & reliability date: ap ril 7, 2006 date: april 7 , 2006
reliability report: sp6330 april 7 , 2006 page 2 of 5 table of contents title page??????????????????????..???i table of contents???????????????????.???ii device description ????????????????..???..?..ii block diagram??? ????????????????????..ii manufacturing information?????????.?????????.iii package information?????????????.????????iii reliability test summary.??????..??????.?????.?iv life test data???????????????????????...iv fit data calculations??????????????????.??.. v mtbf data calculations??????????????...????...v device description: sp6330 - sp6332 - sp6334 quad power supervisory circuit family is a family of microprocessor reset supervisory circuits with multiple reset voltages. the family provides low voltage m onitoring ability for up - to four supplies with two precision factory - set thresholds and two user defined custom thresholds. these circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs ar e asserted. the sp6330, sp6332, and sp6334 are packaged in an 8 - pin tsot package. all devices are fully specified over - 40 o c to +85 o c temperature range. sp 6330 pin out manufacturing information: products: sp6330 description: quad power supervisory cir cuit mask set(s): ms1 512az process: cmos process name: pbc4 wafer manufacturer: polar semiconductor, inc. assembly location: carsem ? malaysia qualification lot #?s: 3522a001a.11, 3638a001.8, 3638a001.6
reliability report: sp6330 april 7 , 2006 page 3 of 5 package information: package type: 8 pin tsot die size: 45 x 67 mil reliability qualification test summary: stress level device burn - in temp sample size no. fail 168hrs sp6330 125 c 240 0 500hrs sp6330 125 c 240 0 1000hrs sp6330 125 c 240 0 life test life testing is conducted to determine if there are any fundamental reliability related failure mechanism(s) present in the device. these failure mechanisms can be divided roughly into four groups: 1. process or die related failures, such as oxide - related defec ts, metalization - related defects and diffusion - related defects. 2. assembly - related defects such as chip mount wire bond or package - related failures. 3. design related defects. 4. miscellaneous, undetermined or application - induced failures. life test results as part of the sipex design qualification program, the engin eering group had subjected 80 parts from each of 3 lots of sp6330 for a 1000 h our reliability life test at 125 c. 168 hour life test 240 parts of sp6330 parts were subjected to the life test pr ofile and completed 168hr the test without any part failures. 500 hour life test
reliability report: sp6330 april 7 , 2006 page 4 of 5 the 240 parts of sp6330 we reintroduced to the second phase of the test, where the parts again showed successfully completing the 500 - hour life test without any failures. 1000 hour life test the 240 parts of the sp6330 were reintroduced to the final phase of the test, where the parts again successfully completed 1000 - hour life test without any shift on the process parameters. fit rate calculations the fit (failures in time) rate is the predicted number of failures per billion device - hours. this predicted value is based upon the: 1. life test conditions (time and temperature, device quantity and number of failures) are summarized under htol test table. 2. activation energy (e a ) of the potential failure modes. the weighted activation energy, e a , of observed failure mechanisms of sipex products has been determined to be 0.8 ev. based on the above criteria, the fit rates at 25 , 55 and 70 c operation at both 60% and 90% conf idence levels for the sp6330 product lines have been calculated and are listed below. fit failure rates sp6330 product confidence level +25 c +55 c +70 c 60% 1.6 26.6 90.8 90% 4.1 68.4 233.1 1 fit = 1 failure per billion device - hours mtbf calculat ion for sp6330 product confidence level +25 c +55 c +70 c 60% 6.30e+08 3.75e+07 1.10e+07 90% 2.46e+08 1.46e+07 4.29e+06
reliability report: sp6330 april 7 , 2006 page 5 of 5 esd testing hbm esd testing - 5 units from each of three lots were subjected to 40 00 v human body model (hbm) esd stress. each pin was subjected to three positive and three negative pulses with respect to ground. all units passed testing after esd stress. latch - up testing - 5 units from each of three lots were subjected to latch - up testing at +/ - 100ma. all units passed.

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